It is well known in the art to perform combined synchronization and error detection/error correction, for example as described in the "Background of the Disclosure" of U.S. Pat. No. 5,084,891, by Ariyavisitakul et al., issued Jun. 28, 1992, to Bell Communications Research, Inc. Ariyavisitakul et al. teach a technique for jointly performing bit synchronization and error detection on a TDMA burst of received digital data. The technique of Ariyavistakul et al. relies on successive addition and deletion of marker bits from a received word coupled with successive polynomial division in a two-pass approach using a common generator polynomial to successively determine timing and error syndrome values for this word.
Specifically, a cyclically redundant codeword that contains a pre-defined number of information bits, followed by a pre-defined number of parity bits, e.g. a (161,147) codeword, is formed for transmission, using e.g. either a TDM packet or TDMA burst for carriage over an error-prone radio link. The parity bits are determined by dividing the information bits by a given binary generator polynomial, g(x). The first and last bits in the codeword are then marked through bit inversion thereof to yield a first set of marker bits.
The resulting codeword is then transmitted to a receiving site. At the receiving site, a two-pass approach is undertaken to recover synchronization of a corresponding received word and to determine whether any bit errors exist therein. Specifically, within the synchronization pass, a second set of marker bits is first inserted into the received word, again through inverting the first and last bits therein. The resulting marked word can then be rotated to the left by a pre-determined number, such as seven, of bit positions to place potentially erroneous bits at the end of this word. A multi-bit timing syndrome value is then determined for the resulting, now rotated, marked word, by dividing this word by the polynomial generator g(x). The timing syndrome value is then used, for example, to access a look-up table to yield a corresponding value of bit slippage. The received word is then shifted, i.e. advanced or retarded, by an amount of bit positions and in a direction specified by the bit slippage value to yield an intermediate word. If excessive bit slippage has occurred in the received word, this slippage can not be corrected. As such, a suitable error signal is provided to instruct a receiver burst processor to ignore this word. At this point, an error detection pass is undertaken on the intermediate word. Within this pass, the first set of marker bits is first removed from the intermediate word to form an unmarked word for which an error syndrome value is then determined through polynomial division of this latter word by the polynomial generator g(x). In the event the error syndrome value is zero, then the unmarked word is provided as a synchronized substantially error-free codeword to a suitable output point, such as a memory location or output lead. Alternatively, if the unmarked word contains one or more bit errors as indicated by a non-zero valued error syndrome, an error signal is also provided to a receiver burst processor to instruct it to ignore this word.
Due to the serial nature of the synchronization and error detection, several delays occur between reception of the data and delivery of the data following synchronization and error detection.